In the modern world of digitization, processing of data in real time requires an increase in the operating speed of a system. The processing more often than not utilizes multiplication which is time consuming and introduces considerable amount of delay. As such, there is a need to reduce this delay and achieve faster real time processing of data. This paper proposes a novel architecture for implementation of signed multiplication using the vedic algorithm. An 11x8 bit multiplier was designed using the proposed architecture and implemented using Xilinx ISE Design Suite 13.2 with Spartan 3E as the target FPGA. The maximum clock speed achieved was 203.938 MHz.

This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva -Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.

Achieving high speed integrated circuits with low power consumption is a major concern for the VLSI circuit designers. Most arithmetic operations are done using multiplier,which is the major power consuming element in the digital circuits. Basically the process of multiplication is realized in hardware in terms of shift and add operation. The optimizationof adder has led to the improvement in performance of multiplier. In this paper, a modified full adder using multiplexer is proposed to achieve low power consumption of multiplier. To analyze the efficiency of proposed design, the conventional Wallace tree multiplier structure is used. The designs are developed using Verilog HDL and the functionalities are verified through simulation using Quartus II. The designs are synthesized in Synopsys Design Compiler using SAED90nm CMOS technology. The ASIC synthesis results of the proposed multiplier shows an average reduction of 37.45% in power consumption, 45.75% in area, and 17.65% in delay compared to the existing approaches.

This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and subtraction on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP numbers and is based on a fully pipelined circuit. The design presents a novel hardware for pre-signal generation stage and an enhanced version of previously published leading zero stage. The design can operate at a frequency of 200 MHZ on a Virtex-5 with a latency of 8 cycles. The presented DFP adder/subtractor supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To our knowledge, this is the first hardware FPGA design for adding and subtracting IEEE 754-2008 using decimal64 encoding.

In the present paper our objective is to emphasize the importance of Vedic Mathematics for digital applications. Ancient vedic mathematics not only facilitate the complex mathematical operations but also useful for logical applications. In the present work we are using the concept of Urdhva-tiryakbyham, i.e., vertically and crosswise multiplication and it’s implementation for 16-bit multiplication. This technique optimizes the output in term of steps of calculation and therefore reduces the delay of a digital circuit. We implemented these results with the help of front end language—Verilog. Results obtained from simulation and syntheses have been verified on Spartan 3E FPGA using Xilinx ISE Suite are discussed in details. Obtained results have been compared with the most frequently used multipliers in digital circuits which illustrate 38 % reduction in device utilization and 62% reduction in delay.

Most of the scientific operation involve floating point computations. It is necessary to implement faster multipliers occupying less area and consuming less power. Multipliers play a critical role in any digital design. Even though various multiplication algorithms have been in use, the performance of Vedic multipliers has not drawn a wider attention. Vedic mathematics involves application of 16 sutras or algorithms. One among these, the Urdhva tiryakbhyam sutra for multiplication has been considered in this work. An IEEE-754 based Vedic multiplier has been developed to carry out both single precision and double precision format floating point operations and its performance has been compared with Booth and Karatsuba based floating point multipliers. Xilinx FPGA has been made use of while implementing these algorithms and a resource utilization and timing performance based comparison has also been made.Keywords:- Vedic multiplication, FPGA, Floating Point

Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. This paper presents a reversible comparator based on prefix tree grouping methodology. The proposed design is realized by cascading three stages. The first stage is a 1-bit reversible comparator which generates ‘greater’ and ‘equal’ signals of that operand bit. These signals are combined using prefix tree grouping logic to generate final ‘greater’ and ‘equal’ signals. Using these final ‘greater’ and ‘equal’ signals, ‘lesser’ signal is generated in the third stage. The design is optimized in quantum level for efficient performance in all the cost metrics. The proposed 64-bit comparator design results in 14.3% reduced quantum delay, 7.8% reduced quantum cost and 25% reduced garbage outputs when compared with the best existing design of prefix based comparator.

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT
CSLA.

CORDIC (Coordinate Rotation Digital Computer) is a simple and efficient algorithm to calculate hyperbolic and trigonometric functions. It is commonly used when no multiplier hardware is available (e.g., simple micro-controllers and FPGAs). The only operations it requires are addition, subtraction, bit shift and lookup table. The pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver is designed.

The design of CORDIC in the vector rotation mode results in high system throughput due to its pipe-lined architecture where latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in the proposed design can be achieved through optimization in the number of micro rotations. For better loop performance of
first order complex DPLL and to minimize quantization error, the number of iterations are also optimized.

CORDIC plural-multiplier is the key module to affecting the speed and accuracy of FFT processor. Considering these demands, the problem of CORDIC algorithm is discussed in detail and the according optimization methods are given in this paper. Then, the hardware pipe-lining structure of the CORDIC multiplier is put forward. Comparison results about RTL simulation results with MATLAB calculation indicate that the design is feasible and practical.

An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant. The implementation of the multiplier module has been done in a top down approach. The sub-modules have been written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E.

Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal processors or on application specific VLSI chips. Coordinate Rotation DIgital Computer (CORDIC) algorithm has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. This paper presents the design of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver. The design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in proposed design can is achieved through optimization in the number of micro rotations. For better loop performance of first order complex DPLL and to minimize quantization error, the numbers of iterations are also optimized.

The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices. For digital realizations the Ordinary Differential Equations (ODE’s) are replaced by a discrete time system. Furthermore numerical values are expressed in a numerical representation. It is well known that these two discretization processes may strongly affect the chaotic behavior of the system. In previous contributions we considered the use of the Euler’s algorithm in two different numerical representations: (a) integer arithmetics and (b) single floating point IEEE-754 standard. For applications that require a good agreement between the analog chaotic system and its digital counterpart, more involved algorithms and/or numerical representations must be used. Guided by numerical simulations, in this paper we propose an improvement replacing the Euler’s algorithm by the fourth order Runge Kutta algorithm (RK4). In order to diminish the required hardware a method based on blocks’ reusing is proposed. The procedure is exemplified on a Lorenz CS. The whole design was implemented onto a FPGA, using only 12 % of its logic elements, 13% of its embedded multipliers and 34% of its memory bits.