In this paper, a low-complexity color interpolation algorithm is proposed for the very-large-scale integration (VLSI) implementation in real-time applications. The proposed novel algorithm consists of an edge detector, an anisotropic weighting model, and a filter-based compensator. The anisotropic weighting model is designed to catch more information in horizontal than vertical directions. The filter-based compensation methodology includes a Laplacian and spatial sharpening filters, which are developed to improve the edge information and reduce the blurring effect. In addition, the hardware cost was successfully reduced by hardware sharing and reconfigurable design techniques.The VLSI architecture of the proposed design achieves 200 MHz with 5.2-K gate counts, and its core area is 64 236 μm2 synthesized by a 0.18-μm CMOS process. Compared with the previous low-complexity techniques, this paper not only reduces gate counts or power consumption by more than 8% or 91.7%, respectively, but also improves the average color peak signal-tonoise ratio quality by more than 1.6 dB.

Edge detection is one of the most important stages in image processing. The Canny edge detection algorithm is most widely used edge detection algorithm because of it advantages. In this paper we present canny edge detection algorithm implemented on Spartan 3E FPGA and developed VGA interfacing for displaying images on the screen. In this paper we have taken 128×128 Image and displayed same on the monitor through FPGA.